Protection against electrostatic discharge (ESD) is of primary concern in integrated circuit development. At present, the two most prevalent approaches for providing ESD protection is by use of n-channel metal-oxide-semiconductor (NMOS) transistor protection and by use of semiconductor-controlled rectifier (SCR) protection.
NMOS protection schemes, wherein a parasitic lateral npn transistor is used as the primary protection device, have been used to protect circuit structure fabricated according to a CMOS process. The NMOS is fabricated according to this process as well, or according to a compatible process, on an integrated circuit. For circuit structure fabricated according to a CMOS process, having a feature size larger than 1 .mu.m, for which ESD protection is sought, the lateral npn has been shown to offer poor ESD performance. Hence, SCR use is the primary approach used to provide ESD protection for CMOS fabricated circuits having a feature size of larger than 1 .mu.m.
On-chip electrostatic discharge devices such as SCRs, exhibit holding voltages (also known as snapback voltages) which in conjunction with an associated increase in current, provide a highly desirable characteristic for discharging high-voltage, transient, electrostatic charges from the bond pads of a semiconductor integrated circuit.
FIG. 1 illustrates a schematic drawing showing the parasitic bipolar devices of a conventional SCR ESD protection circuit. In connection with a high voltage electrostatic charge on bond pad 2, parasitic bipolar pnp transistor 4 turns on after the base-emitter voltage across resistor 6 drops beneath a threshold voltage associated with parasitic bipolar transistor 4. Parasitic bipolar npn transistor 8 turns on and conducts current to circuit ground in connection with the base-emitter voltage across resistor 10 being above an associated threshold voltage. The conduction of parasitic npn transistor 8 causes an additional voltage drop at the base of parasitic pnp transistor 4 which in turn causes parasitic transistor 4 to conduct more rigorously. As the emitter-collector voltage of parasitic transistor 4 begins to decrease via an increasing collector voltage, as a result of the more rigorous conduction, parasitic transistor 8 conducts more rigorously. The simultaneous conduction of transistors 4 and 8 is known as the latch-up condition. Thus, the reinforcing feedback caused by parasitic transistors 4 and 8 during latch-up causes the electrostatic charge at bond pad 2 to be discharged.
With reference to FIG. 2 (and following the arrows) which is a current (I.sub.m) vs. voltage (V.sub.AB) sketch showing the relationship of the current flowing from point A to point B through a resistance R.sub.m (i.e., resistor R.sub.m can represent a resistance through a current and voltage meter), shown in FIG. 1 to the voltage V.sub.AB across points A and B (V.sub.AB =V.sub.m -I*R.sub.m, V.sub.m being the meter supply voltage), very little current flows prior to latch-up. At latch-up, the trigger point of the circuit of FIG. 1 is reached whereby the voltage across points A and B of FIG. 1 drops down to the holding voltage or as it is sometimes called, the snap-back voltage of the circuit. After the holding voltage (snap-back voltage) point, much current is discharged through transistors 4 and 8 as represented by the Im sketch past the snap-back point. Note that the sketch in FIG. 2 is not complete in that it does not show the I-V characteristic during complete discharge of bond pad 2 in FIG. 1. Also that V.sub.m, R.sub.m and I.sub.m are only shown for the sake of explaining the I-V sketch shown in FIG. 2.
FIGS. 3a and 3b represent cross-sectional/schematic drawings of a conventional SCR and a modified lateral SCR (MLSCR) respectively. The primary difference in structure between the conventional SCR and the modified lateral SCR lies in the existence of n+ region 36 at the edge of n-well 24 of FIG. 3b. N+ region 36 allows a lower junction breakdown voltage for the n+/p- junction formed by n+ region 36 and p+ substrate 22, This lower breakdown voltage generally results in a lower trigger voltage for the MLSCR shown in FIG. 3b as compared with the SCR of FIG. 3a. Parasitic npn transistor 8 is formed by n+ region 20, p-doped substrate 22, and n-type well region (n-well) 24. Parasitic pnp transistor 4 is formed by p- substrate 22, n-well region 24 and p+ region 26. N+ region 30 provides contact to n-well 24. Silicon dioxide (SiO.sub.2) provides isolation between the n+ and p+ regions shown. Circuit structure 33, for which ESD protection is sought, is shown connected to bond pad 2. The SCRs shown in FIGS. 3a and 3b usually have a low holding voltage of around 1 to 2 volts. Should this voltage be lower than the power supply voltage Vdd to circuit structure 33, then it will not be possible to discharge a voltage at bond pad 2 to ground since voltage Vdd supplies energy to the SCR to keep the SCR in latch-up. CMOS fabricated processes for the formation of the SCR and circuit structure 33 will likely involve power supply voltages which are higher than the holding voltage associated with the SCR. Consequently, problems may result in the inability to shut off the latch-up condition after an ESD event or after a power surge or spike in circuit structure 33 which, through bond pad 2, sends the SCR into latch-up. This potential latch-up shut-off problem limits the applicability of SCR ESD protection applications. For example, SCR protection is usually not recommended for power supply protection.